In the design of integrated circuits, it is known that designers typically utilize one or more libraries of functional circuit elements, commonly known as “cells,” to design circuits as part of one or more such integrated circuits. These cells are typically standardized in that they have known electrical characteristics such as, for example, propagation delay, capacitance and inductance. A System-on-a-Chip (SoC) is an integrated circuit in which the components needed for a particular system to operate are included on a single semiconductor-based device. Today's SoC designs continue to grow in complexity and performance as technology processes provide greater and greater densities. As such, designers are adopting block-based or hierarchical design methodologies to manage multimillion cell SoC designs, where a block comprises multiple cells that form a designated functional area of the integrated circuit design and/or a designated physical area of the integrated circuit device upon which the design is fabricated. The blocks are connected and/or interact in a design hierarchy. However, as blocks are designed, information about their implementation should be provided for integration of the respective blocks into the overall integrated circuit design. When design of the blocks is complete and the blocks meet their specific design criteria, an overall integrated circuit-level verification process is performed to validate the overall design prior to the tape out process. One part of such overall integrated circuit-level verification process includes performing a crosstalk noise analysis with respect to the hierarchy of blocks in the design, i.e., a hierarchical crosstalk noise analysis. There can be significant challenges in such analysis because there is a dependency between the noise behavior of a given block and the overall integrated circuit environment. As such, effective cell noise models should be generated to accurately account for such dependencies and other parameters.